After the notion of the multi-core processor, we entered the era of manycore processors. These Chips Multi Processor (CMP) are built according to various architectures in terms of ALU, memory architectures, cache memories systems, etc. Simpler architectures are also easier to design and to test. The result is a much more faster Time-To-Market (TTM) and thus a lower cost of design. More complex architectures will allow to optimize the performances of the system at the level of run times as well as the electrical consumption.
This workshop on “Manycore Real time Embedded and Low power consumption” will cover several aspects (the list is non-exclusive) such as Architecture, Programming tools, Library and Applications, with presentations.
The event will take place in Paris on April the 25th. It is co-organise by our partner TCS and the topic is at their core contribution in eWINE.
All information about the event at (French): gdr-isis.fr